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Senior \/ Staff Engineer for SoC Implementation |
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| Senior \/ Staff Engineer for SoC Implementation职位说明及要求 | |
| Job Description Able to comprehend Chip and block level timing constraint and make modification to input in SDC and communicate the change to RTL designer Excellent skills using Tcl scripting to solve placement， clock tree， power routing， signal routing， RLC extraction， timing closure steps. Experience doing Synthesis and Scan synthesis for ATPG run Experience using Magma Blast Create， and Blast Fusion or Synopsys DC， and Astro completed at least 3 SoC projects at complexity of 2 million random logic instances with Analog blocks， Embedded 1 M Memory， and processor such as ARM 9 or ARM 11 Experience with timing closure with On chip variation and Signal Integrity consideration Multiple clock domain - Clock Tree synthesis with function and test modes Multi power domain， Power grid design for IR drop and EM consideration Be able to use Blast rail or Voltage Storm for ID drop and EM analysis Layout verification using Mentor’s Calibre for DRC， ERC， LVS， Antenna rule checks. Good understanding of IO latch up， ESD prevention Requirements: 1. Minimum of 3 – 7 years of synthesis， timing application， automated layout， and timing closure experience in 5 – 10 million gates SoC. 2. MSEE or above， and excellent English language skills 3. Good communication， and be able to work in a dynamic team environment， proactive， self motivated， and a high standard achiever. |
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