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ASICLogicDesignEngineer |
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| ASICLogicDesignEngineer职位说明及要求 | |
Job Description: In this role you will participate in design and implementing structural and gate-level RTL for highly complex digital communication and multimedia ASIC‘s. Responsibilities include micro-architecture definition, logic design, DFT and timing closure; other responsibilities may include block level verification, and FPGA prototyping. Candidate Qualifications: - BS or MS degree in Electrical Engineering or Computer Science - 3-5 years experience in micro-architecture and RTL logic design (Verilog and/or VHDL). - Good knowledge in Synthesis, Static Timing Analysis, Debug - Basic lab skills. Working knowledge of FPGA based prototyping. - Strong software skills (C/C++ programming, low level hardware interface programming) is desired - Strong UNIX scripting skills required, Perl/TCL/bash/csh - Excellent communication and presentation skills - Well organized, methodical, and detail oriented; - Team player, and easy to work with |
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电子邮箱：xiaoyu.wei@availink.com 公司网址： |